The present invention relates to a method of fabricating a semiconductor device, and particularly to a method of fabricating a semiconductor device composed of an insulated gate field effect transistor using a SALICIDE (Self-Aligned Silicidation) technology.
With the trend toward finer-geometries of a semiconductor integrated circuit, a gate length of an insulated gate field effect transistor has come to be shorter and thereby the resistance upon operation of the transistor has come to be lower. However, there is the tendency for the resistance of a contact portion to increase due to a reduction in diameter of the contact portion and for a parasitic resistance to increase due to shallow junction of a diffusion layer. As a result, the problem in terms of a reduction in current driving ability due to the increased parasitic resistance becomes increasingly serious. To reduce such a parasitic resistance, there has been proposed a SALICIDE technology in which a metal is deposited on a silicon based material, followed by heat-treatment to form a silicide of the metal, and the metal is removed with only the silicide left.
The SALICIDE technology will be briefly described below. As shown in FIG. 1A, a gate electrode 114 is formed on a silicon substrate 111 through a gate insulating film 113 in a region between isolation insulating films 112 formed in the silicon substrate 111, and diffusion electrodes 115 and 116 are formed in the silicon substrate 111 on both sides of the gate electrode 114. On both the sides of the gate electrode 114 are also formed side walls 117 and 118. Then, a cobalt film is deposited on the silicon substrate 111 having such a gate structure, followed by heat-treatment for silicidation of cobalt and removal of unreacted cobalt using dilute ammonia, to form a cobalt silicide electrode 121 on the gate electrode 114 and cobalt silicide electrodes 122 and 123 respectively on the diffusion electrodes 115 and 116. According to this method, the cobalt silicide electrode 121 formed on the gate electrode 114 is at the level higher than that of the side walls 117 and 118.
As shown in FIG. 1B, a silicon nitride film 131 is deposited on the silicon substrate 111 in such a manner as to cover the gate electrode 114 and the like, and a silicon oxide film 132 is deposited thereon. Then, as shown in FIG. 1C, contact holes 141 and 142 are opened in the silicon oxide film 132 by a lithography technique and an etching technique by means of which silicon oxide exhibits an etching selectivity to silicon nitride. Then, the silicon nitride film 131 is etched by an etching technique by means of which silicon nitride exhibits an etching selectivity to silicon oxide. In this way, the contact holes 141 and 142 respectively reaching to the cobalt silicide electrodes 122 and 123 are formed.
On the other hand, along with a trend toward finer-geometries of a semiconductor integrated circuit, it has come to be difficult to make larger a distance between a contact portion and a gate electrode, and to cope with such an inconvenience, there has been proposed a SAC (Self-Aligned Contact) technology in which a film formed of a material different from that of an interlayer insulating film is formed on an upper portion and side portions of a gate electrode for preventing a contact portion from being in contact with or close to the gate electrode.
In accordance with the related art SAC process, however, it has been required to deposit an insulating film on a gate electrode for ensuring insulation between a contact portion and the gate electrode before the gate electrode is processed. As a result, for silicidation of a gate electrode as well as source/drain electrodes (for example, a silicon substrate), an insulating film on the gate electrode must be removed before deposition of a metal for silicidation. In this regard, if an insulating film made from a material similar to that of an isolation insulating film is formed on a gate electrode, there occurs a problem that the isolation insulating film is etched upon removal of the insulating film on the gate electrode by etching.
The fabrication method described with reference to FIGS. 1A to 1C presents another problem. If a position of a contact hole is shifted to be overlapped to side walls formed on side walls of a gate electrode, a distance between the gate electrode (particularly, silicide portion) and a contact portion formed in the contact hole is made narrow, to thereby reduce a withstand voltage characteristic.